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IBM OpenPower

Date: 13 October 2015, Tuesday
Time: 10 am - 12.30 pm and 1.30 pm - 3 pm
Venue: Aspiration @ MATRIX Level 2M

Topic Title Speaker Period
1 Overview of the POWER8 Processor and Systems Peter Hofstee , IBM 45 mins
2 (Open)POWER-based Big Data Systems from Watson to Spark Peter Hofstee , IBM 45 mins
3 NVIDIA's GPU accelerator for OpenPOWER Simon See, nVidia 45 mins
4 Reconfigurable acceleration for Big Data and Genomics Peter Hofstee , IBM 45 mins
5 OpenPOWER in Academia and Research Ganesan Narayanasamy , IBM 45 mins


Title: Overview of the POWER8 Processor and Systems

This session will provide an overview of the Power 8 processor and the systems built with Power 8 technology. With 96 hardware threads over twelve cores running at up to 4GHz, 96 MB of on-chip L3, 128 MB of L4, up to 230GB/s of main memory bandwidth, and numerous architectural innovations such as transactional memory, the Power 8 processor provides leading throughput performance. Processor performance is matched by a powerful I/O subsystem with additional innovations such as the Coherent Attach Processor Interface, and a high-bandwidth SMP fabric that scales to a very flat 16-socket, 1,536-thread 16TB SMP. We will also describe how Power 8 technology is leveraged in the OpenPOWER systems, by combining Power 8 technology with that of our OpenPOWER partners such as NVIDIA, Xilinx and Altera, Mellanox, and others for a wide variety of systems from IBM and other system vendors.

Title: (Open)POWER-based Big Data Systems from Watson to Spark

This session will address how we are using Power 8 technology to create leading solutions for analytics and Big Data. We provide a short introduction to the types of problems we aim to solve with Big Data and Analytics, and then discuss how Power 8 is used in systems for Big Data such as Hadoop and Spark. Storage architecture determines a large fraction of the cost of these systems, and we show how Power 8 technology, and accelerators, are used in cost effective storage systems as well as a flash-based Redis key-value store. We also show how the technology can be used to create a high-performance implementation of write logging in Cassandra.

Title: Reconfigurable acceleration for Big Data and Genomics

This session dives a bit deeper on the use of reconfigurable acceleration leveraging the CAPI interface on Power 8. We start by describing a high-performance implementation of gzip compression, an application that at first sight seems difficult to accelerate. Our implementation of gzip in reconfigurable logic achieves up to 4GB/s encode and decode speeds ( at the macro level ) and a latency of just a few microseconds per 4KB page. Next we discuss how CAPI has been leveraged to accelerate gene sequencing. We describe the benefits of acceleration for each of the three major stages of the pipeline ( alignment, duplicate removal, and variant calling ). We also describe the CAPI-flash implementation in a bit more detail, and discuss its various APIs. Next we touch on some image processing work, and look ahead at our next set of opportunities and challenges for acceleration. We end with a description of accelerated cloud-based infrastructure that can freely be leveraged by OpenPOWER members ( and academic membership is free ).

Title: OpenPOWER in Academia and Research

We will be sharing the up to date information on Universities who involve in OPEN POWER related projects and research collaborations . What resources available for research and collaboration at Universities around the world which will help to develop and build skills. Will share a list of the ongoing Academia OPENPOWER Projects, the details of operation model for academic member to contribute to the projects. Also details about current Academia Workgroup members and various activities.


Speaker: H. Peter Hofstee ( Ph.D. California Inst. of Technology, 1995 )

H. Peter Hofstee is a distinguished research staff member at the IBM Austin Research Laboratory, USA, and a part-time professor in Big Data Systems at Delft University of Technology, Netherlands. Peter is best known for his contributions to heterogeneous computer architecture as the chief architect of the Synergistic Processor Elements in the Cell Broadband Engine processor, used in the Sony Playstation3 and the first supercomputer to reach sustained Petaflop operation. After returning to IBM research in 2011 he has focused on optimizing the system roadmap for big data, analytics, and cloud, including the use of accelerated compute. His early research work on coherently attached reconfigurable acceleration on Power 7 paved the way for the new coherent attach processor interface on POWER 8. Peter is an IBM master inventor with more than 100 issued patents and a member of the IBM Academy of technology.

Speaker: Ganesan Narayanasamy

Ganesan Narayanasamy is an OpenPOWER leader for Academia and research at the IBM Lab. Ganesan is best known for his contributions to High Performance Computing as senior leader for nearly 1.5 decades. He is also leading the WW Academia workgroup for OpenPOWER and putting together OpenPOWER ECO System development activities like setting up OpenPOWER center of excellence, OpenPOWER labs, Curriculum development etc. Ganesan is always passionate about working with Universities and research Institutes and provide all kinds of technical support.

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Last Updated - 30th Sep 2015
 
     
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